# Shift registers - special features

Some shift registers have the following features:

- Parallel output : The data at all (or at least many) stages is displayed on output pins.
- Parallel input : Data can be loaded in parallel into all stages from input pins commonly labelled 'P0', 'P1', ... by triggering the parallel load pin 'LD'.
- Reset : The reset pin 'R' is used to set the data at all stages to zero.

## See also:

- Shift registers
- Logic family parts
- Simulation of Digital ICs